#
#Copyright (c) 2024 Black Sesame Technologies
#
#Licensed under the Apache License, Version 2.0 (the "License");
#you may not use this file except in compliance with the License.
#You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
#Unless required by applicable law or agreed to in writing, software
#distributed under the License is distributed on an "AS IS" BASIS,
#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#See the License for the specific language governing permissions and
#limitations under the License.
#

# config default build output folder
BUILD_DIR := build

# config architecture type (ARM9/A55/R5/RISC_V/...)
#ARCH := A55
#ARCH := M0
#ARCH := R5_SECURE
#ARCH := R5_SAFETY
#ARCH := R5_REALTIME
ARCH := R5_SWITCH_CPU2
CHIP := C1200

#TEST_ENV := ZEBU
TEST_ENV := CHIP


# config optimization level
OLEVEL := O2

# config memory to store log(MEM_LOG_START~MEM_LOG_END), if do not set MEM_LOG_START indicate do not store log to memory
MEM_LOG_START := 
MEM_LOG_END := 

# config malloc heap memory
MAL_HEAP_START := 0x30004000
MAL_HEAP_END := 0x30008000

# config stack head(downgrowth stack)
STACK_HEAD_ADDR := 4096

# config start VMA address
VMAADDR :=

#select an uart for xtor<->dut sync: 0(disable), 1(uart0), 2(uart1), 3(uart2), 4(uart3)
BST_UART_SYNC := 4


# please select only 1 test module to test: unmask(remove #) the module select
module_test += gic
module_test += r5_clk
module_test += hscg_firmware
module_test += wdt